Determining the location of the ModelSim executable...

Using: /home/zaz/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Compteur_8_Chiffres_Verilog -c Compteur_8_Chiffres_Verilog --vector_source="/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/Waveform1.vwf" --testbench_file="/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim/Waveform1.vwf.vt"

Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.    Info: Your use of Intel Corporation's design tools, logic functions     Info: and other software and tools, and its AMPP partner logic     Info: functions, and any output files from any of the foregoing     Info: (including device programming or simulation files), and any     Info: associated documentation or information are expressly subject     Info: to the terms and conditions of the Intel Program License     Info: Subscription Agreement, the Intel Quartus Prime License Agreement,    Info: the Intel FPGA IP License Agreement, or other applicable license    Info: agreement, including, without limitation, that your use is for    Info: the sole purpose of programming logic devices manufactured by    Info: Intel and sold by Intel or its authorized distributors.  Please    Info: refer to the applicable agreement for further details.    Info: Processing started: Wed Apr  3 14:20:01 2019Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Compteur_8_Chiffres_Verilog -c Compteur_8_Chiffres_Verilog --vector_source=/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/Waveform1.vwf --testbench_file=/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim/Waveform1.vwf.vtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully. 

Completed successfully. 

**** Generating the timing simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim/" Compteur_8_Chiffres_Verilog -c Compteur_8_Chiffres_Verilog

Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.    Info: Your use of Intel Corporation's design tools, logic functions     Info: and other software and tools, and its AMPP partner logic     Info: functions, and any output files from any of the foregoing     Info: (including device programming or simulation files), and any     Info: associated documentation or information are expressly subject     Info: to the terms and conditions of the Intel Program License     Info: Subscription Agreement, the Intel Quartus Prime License Agreement,    Info: the Intel FPGA IP License Agreement, or other applicable license    Info: agreement, including, without limitation, that your use is for    Info: the sole purpose of programming logic devices manufactured by    Info: Intel and sold by Intel or its authorized distributors.  Please    Info: refer to the applicable agreement for further details.    Info: Processing started: Wed Apr  3 14:20:02 2019Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory=/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim/ Compteur_8_Chiffres_Verilog -c Compteur_8_Chiffres_VerilogWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file Compteur_8_Chiffres_Verilog_8_1200mv_85c_slow.vo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo (204019): Generated file Compteur_8_Chiffres_Verilog_8_1200mv_0c_slow.vo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo (204019): Generated file Compteur_8_Chiffres_Verilog_min_1200mv_0c_fast.vo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo (204019): Generated file Compteur_8_Chiffres_Verilog.vo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo (204019): Generated file Compteur_8_Chiffres_Verilog_8_1200mv_85c_v_slow.sdo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo (204019): Generated file Compteur_8_Chiffres_Verilog_8_1200mv_0c_v_slow.sdo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo (204019): Generated file Compteur_8_Chiffres_Verilog_min_1200mv_0c_v_fast.sdo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo (204019): Generated file Compteur_8_Chiffres_Verilog_v.sdo in folder "/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning    Info: Peak virtual memory: 1064 megabytes    Info: Processing ended: Wed Apr  3 14:20:04 2019    Info: Elapsed time: 00:00:02    Info: Total CPU time (on all processors): 00:00:01
Completed successfully. 

**** Generating the ModelSim .do script ****

/media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim/Compteur_8_Chiffres_Verilog.do generated.

Completed successfully. 

**** Running the ModelSim simulation ****

/home/zaz/intelFPGA_lite/18.1/modelsim_ase/linuxaloem//vsim -c -do Compteur_8_Chiffres_Verilog.do

Reading pref.tcl
# 10.5b
# do Compteur_8_Chiffres_Verilog.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 14:20:05 on Apr 03,2019# vlog -work work Compteur_8_Chiffres_Verilog.vo 
# -- Compiling module Compteur_8_Chiffres_Verilog
# -- Compiling module hard_block
# # Top level modules:# 	Compteur_8_Chiffres_Verilog# End time: 14:20:05 on Apr 03,2019, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 14:20:05 on Apr 03,2019# vlog -work work Waveform1.vwf.vt 
# -- Compiling module Compteur_8_Chiffres_Verilog_vlg_vec_tst
# 
# Top level modules:# 	Compteur_8_Chiffres_Verilog_vlg_vec_tst# End time: 14:20:05 on Apr 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Compteur_8_Chiffres_Verilog_vlg_vec_tst # Start time: 14:20:05 on Apr 03,2019# Loading work.Compteur_8_Chiffres_Verilog_vlg_vec_tst# Loading work.Compteur_8_Chiffres_Verilog# Loading work.hard_block# Loading cycloneive_ver.cycloneive_io_obuf# Loading cycloneive_ver.cycloneive_io_ibuf# Loading cycloneive_ver.cycloneive_clkctrl# Loading cycloneive_ver.cycloneive_mux41# Loading cycloneive_ver.cycloneive_ena_reg# Loading altera_ver.dffeas# Loading cycloneive_ver.cycloneive_lcell_comb# SDF 10.5b Compiler 2016.10 Oct  5 2016# Loading instances from Compteur_8_Chiffres_Verilog_v.sdo# Loading altera_ver.PRIM_GDFF_LOW# Loading timing data from Compteur_8_Chiffres_Verilog_v.sdo# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.#    Time: 0 ps  Iteration: 0  Instance: /Compteur_8_Chiffres_Verilog_vlg_vec_tst File: Waveform1.vwf.vt
# after#26
# ** Warning: (vsim-3116) Problem reading symbols from linux-gate.so.1 : can not open ELF file.# ** Note: $finish    : Waveform1.vwf.vt(56)#    Time: 1 us  Iteration: 0  Instance: /Compteur_8_Chiffres_Verilog_vlg_vec_tst
# End time: 14:20:05 on Apr 03,2019, Elapsed time: 0:00:00# Errors: 0, Warnings: 1
Completed successfully. 

**** Converting ModelSim VCD to vector waveform ****

Reading /media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/Waveform1.vwf...

Reading /media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim/Compteur_8_Chiffres_Verilog.msim.vcd...

Processing channel transitions... 

Writing the resulting VWF to /media/4TB_BACKUP/ZAZDISK_D/Proj/Bidouilleur/FPGA_Eval_Board/Compteur_8_Chiffres_Verilog/simulation/qsim/Compteur_8_Chiffres_Verilog_20190403142005.sim.vwf

Finished VCD to VWF conversion.

Completed successfully. 

All completed.